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1 ?2004 integrated device technology, inc. march 2004 dsc 5681/2 idt70p5258ml idt70p525ml idt70v525ml features high-speed access ? industrial: 55ns (max.) low-power operation ? idt70p5258ml and idt70p525ml active: 54mw (typ.) standby: 7.2 w (typ.) ? idt70v525ml active: 450mw (typ.) standby: 250 w (typ.) functional block diagram high-speed 8k x 16 triport static ram r/ w p1 be 0p1, be 1p1 oe p1 i/o 0p1 -i/o 15p1 a 0p1 -a 11p1 r/ w p2 ce p2 oe p2 i/o 0p2 -i/o 15p2 a 0p2 -a 11p2 memory array port 1 i/o control port 1 address decode r/ w p1 oe p1 port 2 i/o control port 3 i/o control 5681 drw 01 r/ w p3 ce p3 oe p3 i/o 0p3 -i/o 15p3 a 0p3 -a 11p3 , port 2 address decode port 3 address decode interrupt control ce p2, ce p3 oe p2, oe p3 r/ w p2, r/ w p3 int p1 - p2 int p1 - p3 be 0p1, be 1p1 int p3 - p1 int p2 - p1 be 0p1, be 1p1 triport architecture allows simultaneous access to the memory from all three ports fully asynchronous operation from each of the three ports: p1, p2, and p3 idt70p5258 supports 3.0v and 1.8v i/o's available in 144-ball 0.5mm-pitch fp bga industrial temperature range (?40c to +85c)
6.42 idt70x525xml preliminary low power 4k x 8 triport static ram industrial temperature range 2 notes: 1. v ddq for 70p5258. pin configurations (1,2,3) description the idt70x525x is a high-speed 8k x 16 triport static ram designed to be used in systems where multiple access into a common ram is required. this triport static ram offers increased system performance in multiprocessor systems that have a need to communicate in real time and also offers added benefit for high-speed systems in which multiple access is required in the same cycle. the idt70x525x is also designed to be used in systems where on- chip hardware port arbitration is not needed. this part lends itself to those systems which cannot tolerate wait states or are designed to be able to externally arbitrated or withstand contention when more than one port simultaneously accesses the same triport ram location. the idt70x525x provides three independent ports with separate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. it is the user?s responsibility to ensure data integrity when simultaneously accessing the same memory location from mutiple ports. an automatic power down feature, controlled by be 0 and be 1 on port 1 and ce on port 2 and on port 3, permits the on-chip circuitry of each port to enter a very low power standby power mode. the idt70x525x is packaged in a 144-ball 0.5mm-pitch fp bga. j9 j10 k9 k10 j1 j2 j3 j4 k1 k2 k3 k4 j5 j6 j7 j8 k5 k6 k7 k8 a 2p1 a 1p1 a 0p1 a 3p1 a 10p1 i/o 4p1 i/o 0p1 i/o 3p1 i/o 2p1 i/o 1p1 j11 j12 k11 k12 v dd v dd vss vss vss vss v dd vss vss v dd v dd v dd c10 a9 d9 c9 b9 d10 a10 b10 e9 e10 f9 f10 g9 g10 h9 h10 d8 c8 c7 b8 a8 d7 b7 a7 b6 c6 d6 a5 b5 c5 d5 a4 b4 c4 d4 a3 b3 c3 d3 d2 c2 b2 a2 a1 b1 c1 d1 e1 e2 e3 e4 f1 f2 f3 f4 g1 g2 g3 g4 h1 h2 h3 h4 a6 e5 e6 e7 e8 f5 f6 f8 g5 g6 g7 g8 h5 h6 h7 h8 f7 5681 drw 02 , 12/19/03 vss vss vss vss vss vss r/ w p2 oe p2 v dd (1) nc v dd c12 a11 d11 c11 b11 d12 a12 b12 e11 e12 f11 f12 g11 g12 h11 h12 vss vss nc i/o 15p2 i/o 12p2 i/o 11p2 i/o 14p2 i/o 13p2 i/o 8p2 i/o 4p2 i/o 0p2 i/o 3p2 i/o 10p2 i/o 7p2 i/o 9p2 i/o 6p2 i/o 5p2 i/o 2p2 i/o 1p2 i/o 15p3 i/o 12p3 i/o 11p3 i/o 14p3 i/o 13p3 i/o 8p3 i/o 4p3 i/o 0p3 i/o 3p3 i/o 10p3 i/o 7p3 i/o 9p3 i/o 6p3 i/o 5p3 i/o 2p3 i/o 1p3 r/ w p3 oe p3 a 5p2 a 8p2 a 11p2 a 6p2 a 2p2 a 1p2 a 0p2 a 3p2 a 7p2 a 9p2 a 4p2 a 10p2 a 5p3 a 8p3 a 11p3 a 6p3 a 2p3 a 1p3 a 0p3 a 3p3 a 7p3 a 9p3 a 4p3 a 10p3 ce p3 ce p2 v dd (1) v dd (1) v dd v dd vss vss vss vss vss vss vss v dd v dd (1) v dd vss vss vss v dd v dd a 5p1 a 8p1 a 11p1 a 6p1 a 7p1 a 9p1 a 4p1 be 0p1 r/ w p1 oe p1 i/o 15p1 i/o 12p1 i/o 11p1 i/o 14p1 i/o 13p1 i/o 8p1 i/o 10p1 i/o 7p1 i/o 9p1 i/o 6p1 i/o 5p1 v dd l9 l10 m9 m10 l1 l2 l3 l4 m1 m2 m3 m4 l5 l6 l7 l8 m5 m6 m7 m8 l11 l12 m11 m12 be 1p1 nc int p3p1 int p2p1 int p1p3 int p1p2 v dd (1) 70(p/v)525xbz bz-144 top view
6.42 idt70x525xml preliminary low power 4k x 8 triport static ram industrial temperature range 3 pin configurations (1,2) notes: 1. all v dd pins must be connected to the power supply. 2. all v ss pins must be connected to the ground supply. 3. idt70p5258 only. 4. for port 2 and port 3. symbol pin name a 0p1 - a 11p1 address lines - port 1 (input) a 0p2 - a 11p2 address lines - port 2 (input) a 0p3 - a 11p3 address lines - port 3 (input) i/o 0p1 - i/o 15p1 data i/o - port 1 i/o 0p2 - i/o 15p2 data i/o - port 2 i/o 0p3 - i/o 15p3 data i/o - port 3 r/ w p1 read/write - port 1 (input) r/ w p2 read/write - port 2 (input) r/ w p3 read/write - port 3 (input) ce p2 chip enable - port 2 (input) ce p3 chip enable - port 3 (input) oe p1 output enable - port 1 (input) oe p2 output enable - port 2 (input) oe p3 output enable - port 3 (input) be 0p1 bank enable 0 - port 1 (input) be 1p1 bank enable 1 - port 1 (input) int p1 - p2 inte rrupt p1 - p2 - port 1 (output) int p1 - p3 inte rrupt p1 - p3 - port 1 (output) int p2 - p1 inte rrupt p2 - p1 - port 2 (output) int p3 - p1 inte rrupt p3 - p1 - port 3 (output) v dd power (input) v ddq port power supply (input) (3,4) v ss ground (input) 5681 tbl 01
6.42 idt70x525xml preliminary low power 4k x 8 triport static ram industrial temperature range 4 absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v dd + 10% for port 1 or v ddq + 10% for port 2 and port 3 for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > v dd + 10% (port 1) or v ddq + 10% (port 2 and port 3). symbol rating industrial unit v term (2) te rm i n a l vo l t a g e with re sp ec t to gnd -0.5 to v ddmax + 0.3v v t bias temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c t jn junction temperatue +150 o c i out (for 70v525) dc output current 50 ma i out (for 70p525 and 70p5258) dc output current 20 ma 5681 tbl 05 maximum operating temperature and supply voltage (1) notes: 1. this is the parameter t a . this is the "instant on" case temperature. grade ambient temperature device v ss v dd industrial -40c to +85c 70p525 70p5258 0v 1.8v + 100mv 70v525 0v 3.0v + 300mv 5681 tbl 04 notes: 1. this parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and the output signals switch from 0v to 3v or from 3v to 0v. capacitance (1) (t a = +25c, f = 1.0mhz) symbol parameter port conditions (2) max unit c in inp ut capacitance port 1 v in = 3dv 18 pf port 2 & 3 v in = 3dv 9pf c out output capacitance port 1 v out = 3dv 20 pf port 2 & 3 v out = 3dv 11 pf 5681 tbl 03 notes: 1. the supply voltage for all ports on the idt70p525 and idt70v525 is supplied by v dd so there are no v ddq pins on these devices. 2. v il > -1.5v for pulse width less than 10ns. 3. v term must not exceed v dd + 10% for port 1 or v ddq + 10% for port 2 and port 3. recommended dc operating conditions symbol device port parameter min. typ. max. unit v dd 70p5258 all supply voltage 1.7 1.8 1.9 v 70p525 1.7 1.8 1.9 70v525 2.7 3 3.3 v ddq 70p5258 port 2 & 3 i/o supply voltage (1) 2.733.3 v 70p525 n/a ____ ____ ____ 70v525 n/a ____ ____ ____ v ss allallground 000v v ih 70p5258 port 1 input hig h voltag e 1.2 ____ v dd +0.2 v port 2 & 3 2 ____ v ddq +0.2 70p525 all 1.2 ____ v dd +0.2 70v525 all 2 ____ v dd +0.2 v il 70p5258 port 1 input low vo ltag e -0.2 ____ 0.4 v port 2 & 3 -0.2 ____ 0.6 70p525 all -0.2 ____ 0.4 70v525 all -0.2 ____ 0.6 5681 tbl 02
6.42 idt70x525xml preliminary low power 4k x 8 triport static ram industrial temperature range 5 dc electrical characteristics over the operating temperature and supply voltage range (1,4) 70p5258 70p525 ind'l only 70v525 ind'l only symbol parameter test condition version typ. (1) max. typ. (1) max. unit i dd dynamic operating current (both ports active - cmos level inputs) ce = v il , outputs open f = f max (2) ind'l l 30 50 150 180 ma i sb1 standby current (both ports - cmos level inputs ) ce r and ce l = v ih f = f max (2) ind'l l .004 .016 5 10 ma i sb2 standby current (one port - cmos level inputs ) ce " a " = v il and ce " b " = v ih (3) , active port outputs open f = f max (2) ind'l l 17 28 90 110 ma i sb3 full standby current (both ports - cmos level inputs) both ports ce l and ce r > v dd - 0.2v, v in > v dd - 0.2v or v in < 0.2v f = f max (2) ind'l l 41684150 a i sb4 standby current (one port - cmos level inputs ) ce "a" < 0.2v and ce "b" > v dd - 0.2v (3) v in > v dd - 0.2v or v in < 0.2v, active port outputs open f = f max (2) ind'l l 17 28 90 110 ma 5681 tbl 06 notes: 1. v dd = 1.8v for 70p5258 and 70p525. v dd = 3.0v for 70v525, t a = +25c, and are not production tested. i dd dc = 15ma ( typ .) 2. at f = f max , address and control lines are cycling at the maximum frequency read cycle of 1/t rc , and using ?ac test conditions?. 3. for the 70p5258, if port "a" is port 1 then port "b" may be either port 2 or port 3. if port "a" is either port 2 or port 3, port "b" must be port 1. 4. v dd = 1.8v + 100mv for 70p525 and 70p5258. v dd = 3.0v + 300mv for 70v525. note: 1. at v dd < 2.0v input leakages are undefined. 2. v dd = 1.8v + 100mv for 70p525 and 70p5258. v dd = 3.0v + 300mv for 70v525. dc electrical characteristics over the operating temperature and supply voltage range (2) symbol device port parameter test conditions min. max. unit i li 70p5258 all input leakage current v dd = 1.8v, v in = 0v to v dd ____ 1 a 70p525 all v dd = 1.8v, v in = 0v to v dd ____ 1 70v525 all v dd = 3.0v, v in = 0v to v dd ____ 1 i lo 70p5258 all output leakage current ce x = be x = v ih , v out = 0v to v dd ____ 1 a 70p525 all ce x = be x = v ih , v out = 0v to v dd ____ 1 70v525 all ce x = be x = v ih , v out = 0v to v dd ____ 1 v ol 70p5258 port 1 output low voltage i ol = +0.1ma ____ 0.2 v port 2 & 3 i ol = +2ma ____ 0.4 70p525 all i ol = +0.1ma ____ 0.2 70v525 all i ol = +2ma ____ 0.4 v oh 70p5258 port 1 output high voltage i oh = -0.1ma 1.4 ____ v port 2 & 3 i oh = -2ma 2.1 ____ 70p525 all i oh = -0.1ma 1.4 ____ 70v525 all i oh = -2ma 2.1 ____ 5681 tbl 07
6.42 idt70x525xml preliminary low power 4k x 8 triport static ram industrial temperature range 6 ac test conditions input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v/gnd to 1.8v 3ns max. 1.5v/0.9v 1.5v/0.9v figures 1, 2 and 3 5681 tbl 08 timing waveform of read cycle no. 1, any port (1) note: 1. r/ w = v ih and ce (or be x ) = v il . 5681 drw 07 t aa t oh t oh data out address t rc data valid previous data valid , data out 3.3v 435 ? 590 ? 30pf 5681 drw 05 figure3. ac output test load for the 70v525 (for t hz , t lx , t wz , t ow ) figure 1. ac output test load for the 70p525 and 70p5258 r1 r2 30pf (1) 3.0v / 1.8v 5681 drw 04 3.0v 1.8v r1 1022 ? 13500 ? r2 729 ? 10800 ? 5681 tbl 09 5681 drw 06 data out 3.3v 435 ? 590 ? 5pf figure 2. ac output test load for the 70v525
6.42 idt70x525xml preliminary low power 4k x 8 triport static ram industrial temperature range 7 timing waveform of read cycle no. 2, any port (1, 2) notes: 1. r/ w = v ih for read cycles. 2. addresses valid prior to or coincident with ce (or be x) transition low. 3. ce for port 2 or port 3, be x for port 1. 4. timing depends on which signal is asserted last, ce (or be x) or oe . 5. timing depends on which signal is deasserted first, ce (or be x) or oe . ac electrical characteristics over the operating temperature and supply voltage notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. this parameter is guaranteed by device characterization but is not production tested. 70x525x ind'l only symbol parameter min. max. unit read cycle t rc read cycle time 55 ____ ns t aa address access time ____ 55 ns t ace chip enable access time ____ 55 ns t aoe output enable access time ____ 30 ns t oh output hold from address change 5 ____ ns t lz output low-z time (1,2) 5 ____ ns t hz output high-z time (1,2) ____ 25 ns t pu chip enable to power up time (2) 0 ____ ns t pd chip disable to power down time (2) ____ 55 ns 5681 tb10 t lz t aoe 5681 drw 08 t hz data out ce xor be x (3) t ace valid data oe current i cc i sb t pu 50% t pd 50% , (4) (5)
6.42 idt70x525xml preliminary low power 4k x 8 triport static ram industrial temperature range 8 ac electrical characteristics over the operating temperature and supply voltage notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. this parameter is guaranteed by device characterization but is not production tested. 70x525x ind'l only symbol parameter min. max. unit write cycle t wc write cycle time 55 ____ ns t ew chip enable to end-of-write 45 ____ ns t aw address valid to end-of-write 45 ____ ns t as address set-up time 0 ____ ns t wp write pulse width (3) 40 ____ ns t wr write recovery time 0 ____ ns t dw data valid to end-of-write 30 ____ ns t hz output high-z time (1,2) ____ 25 ns t dh data hold time 0 ____ ns t wz write enable to output in high-z (1,2) ____ 25 ns t ow output active from end-of-write (1,2) 0 ____ ns 5681 tbl 11
6.42 idt70x525xml preliminary low power 4k x 8 triport static ram industrial temperature range 9 5681 drw 10 t aw t as t wr t dw data in address t wc r/ w t ew t dh (6) (2) (3) , ce or be x timing waveform of write cycle no. 1, r/ w controlled timing (5) timing waveform of write cycle no. 2, ce controlled timing (1,5) notes: 1. r/ w or ce (or be x) = v ih during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of a ce (or be x) = v il and a r/ w = v il . 3. t wr is measured from the earlier of ce (or be x) or r/ w = v ih to the end of write cycle. 4. during this period, the i/o pins are in the output state, and input signals must not be applied. 5. if the ce (or be x) low transition occurs simultaneously with or after the r/ w = v il transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal is asserted last, ce (or be x) or r/ w . 7. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 3). this parameter is guarant eed but is not production tested. ce or be x 5681 drw 09 t aw t wr t dw data in r/ w t wp data out t wz (7) (4) (4) (2) t ow (7) t hz t lz (7) t hz (3) t dh (6) t as address t wc
6.42 idt70x525xml preliminary low power 4k x 8 triport static ram industrial temperature range 10 ac electrical characteristics over the operating temperature and supply voltage range 70x525x ind'l only symbol parameter min. max. unit interrupt timing t as address set-up time 0 ____ ns t wr write recovery time 0 ____ ns t ins interrupt se t time ____ 45 ns t inr interrupt re set time ____ 45 ns 5681 tbl 12 waveform of interrupt timing (1) 5681 drw 12 addr "a" interrupt set address ce "a" or be x?a? r/ w "a" t as t wc t wr (3) (4) t ins (3) int "b" (2) , 5681 drw 13 addr "b" interrupt clear address oe "b" t as t rc (3) t inr (3) int "b" (2) , ce ?b? or be x ?b? notes: 1. if port a is port 1, port b may be either port 2 or port 3. if port a is either port 2 or port 3, port b must be port 1. 2. see interrupt truth table ii. 3. timing depends on which enable signal ( ce or r/ w ) is asserted last. 4. timing depends on which enable signal ( ce or r/ w ) is de-asserted first.
6.42 idt70x525xml preliminary low power 4k x 8 triport static ram industrial temperature range 11 functional description the idt70x525x provides three ports with separate control, address, and i/o pins that permit independent access for reads or writes to the two banks of memory. these devices have an automatic power down feature controlled by be 0 and be 1 on port 1 and ce on port 2 and port 3. the ce (or be x ) controls on-chip power down circuitry that permits the respective port to go into standby mode when not selected ( ce or be x = v ih ). when port 1 is enabled, it has access to the full memory. when port 2 is active it has access to bank 1 of the memory. when port 3 is active it has access to bank 2 of the memory. see truth table i for a description of the read/write operation. truth table i C read/write control note: 1. both be 0 , and be 1 cannot be active ( be x = v il ) simultaneously. 2. memory bank 0 for port 2. memory bank 1 for port 3. be 0 be 1 r/ w ce oe d 0- d 15 function port 1 hhxxxzport deselected lhlxxdata in data on p ort written into me mory bank 0 lhhxldata out data in memory bank 0 output on port hllxxdata in data on p ort written into me mory bank 1 hlhxldata out data in memory bank 1 output on port xxxxhzoutputs disabled llxxxxnot allowed port 2 or port 3 x x x h x z port deselected xxllxdata in data on p ort written into me mory bank (2) xxhlldata out data in memory bank (2) output on port xxxxhzoutputs disabled hhx hxz be 0 = be 1 = ce p 3 = v ih , sleep mode 5681 tbl 13
6.42 idt70x525xml preliminary low power 4k x 8 triport static ram industrial temperature range 12 port 1 port 2 or 3 function r/ wbe 0 be 1 oe a 11 - a 0 int p 1 - p 2 int p 1 - p 3 r/ wce oe a 11 - a 0 int p x - p 1 l l h x fff x x x x x x l set p2 int flag xxxx x x x xllfff h reset p2 int flag l h l x fff x x x x x x l set p3 int flag xxxx x x x xllfff h reset p3 int flag xxxx x l x llxffe x set p1 int p1-p2 flag (1) xlhlffe h x xxx x x reset p1 int p1-p2 flag xxxx x x l llxffe x set p1 int p1-p3 flag (2) xhllffe x h xxx x x reset p1 int p1-p3 flag 5681 tbl 14 truth table ii - interrupt flag note: 1. port 2 sets the int p 1 - p 2 flag on port 1 so all signals refer to port 2. 2. port 3 sets the int p 1 - p 3 flag on port 1 so all signals refer to port 3. interrupts if the user chooses the interrupt function, a memory location (mailbox or message center) is assigned to each port. interrupt p 1 - p 2 of port 1 ( int p 1 - p 2 ) is asserted when port 2 writes to memory location ffe(hex), where a write is defined as ce = r/ w = v il per truth table ii. port 1 clears the interrupt by accessing address location ffe when be 0 = v il , r/ w is a "don't care". interrupt p 1 - p 3 of port 1 ( int p 1 - p 3 ) is asserted when port 3 writes to memory location ffe (hex), where a write is defined as ce = r/ w = v il . port 1 clears the interrupt by accessing address location ffe when be 1 = v il , r/ w is a "don't care". port 2's interrupt flag ( int p 2 - p 1 ) is asserted when port 1 writes to memory location fff (hex), where a write is defined as be 0 = r/ w = v il . port 2 clears the interrupt by accessing address location fff when ce = v il , r/ w is a "don't care". likewise, port 3's interrupt flag ( int p 3 - p 1 ) is asserted when port 1 writes to memory location fff (hex), where a write is defined as be 1 = r/ w = v il . port 3 clears the interrupt by accessing address location fff when ce = v il , r/ w is a "don't care".
6.42 idt70x525xml preliminary low power 4k x 8 triport static ram industrial temperature range 13 ordering information a power 999 speed a package a process/ temperature range bz 144-ball ball grid array (bz144-1) speed in nanoseconds low power 128k (8k x 16) triport ram industrial only 55 xxxx device type idt 5681 drw 14 l 70p5258 70p525 70v525 the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 10/14/03: initial datasheet 03/23/04: page 7 corrected t oh spec min to 5ns in ac electrical characteristicstable 10 corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 831-754-4613 santa clara, ca 95054 fax: 408-492-8674 dualporthelp@idt.com www.idt.com

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